HD6432351 Datasheet, PDF (107/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

4.5 Trap Instruction
Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction
exception handling can be executed at all times in the program execution state.
The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector
number from 0 to 3, as specified in the instruction code.
Table 4-5 shows the status of CCR and EXR after execution of trap instruction exception
handling.
Table 4-5 Status of CCR and EXR after Trap Instruction Exception Handling
Interrupt Control Mode
I
0
1
2
1
Legend
1: Set to 1
0: Cleared to 0
—: Retains value prior to execution.
CCR
UI
—
—
I2 to I0
—
—
EXR
T
—
0
87