HD6432351 Datasheet, PDF (351/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

9.3.2 Register Configuration
Table 9-4 shows the port 2 register configuration.
Table 9-4 Port 2 Registers
Name
Abbreviation
Port 2 data direction register
P2DDR
Port 2 data register
P2DR
Port 2 register
PORT2
Note: * Lower 16 bits of the address.
R/W Initial Value
W
H'00
R/W H'00
R
Undefined
Address*
H'FEB1
H'FF61
H'FF51
Port 2 Data Direction Register (P2DDR)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
P2DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 2. P2DDR cannot be read; if it is, an undefined value will be read.
Setting a P2DDR bit to 1 makes the corresponding port 2 pin an output pin, while clearing the bit
to 0 makes the pin an input pin.
P2DDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its
prior state after a manual reset, and in software standby mode. As the PPG and TPU are initialized
by a manual reset, the pin states are determined by the P2DDR and P2DR specifications.
Port 2 Data Register (P2DR)
Bit
:
Initial value :
R/W
:
7
P27DR
0
R/W
6
P26DR
0
R/W
5
P25DR
0
R/W
4
P24DR
0
R/W
3
P23DR
0
R/W
2
P22DR
0
R/W
1
P21DR
0
R/W
0
P20DR
0
R/W
P2DR is an 8-bit readable/writable register that stores output data for the port 2 pins (P2₇ to P2₀).
P2DR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior
state after a manual reset, and in software standby mode.
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