HD6432351 Datasheet, PDF (873/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

NDERH — Next Data Enable Registers H
NDERL — Next Data Enable Registers L
NDERH
H'FF48
H'FF49
PPG
PPG
Bit
:
7
6
5
4
3
2
1
0
NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8
Initial value :
0
0
0
0
0
0
0
0
Read/Write : R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
NDERL
Pulse Output Enable/Disable
0 Pulse outputs PO15 to PO8 are disabled
1 Pulse outputs PO15 to PO8 are enabled
Bit
:
Initial value :
Read/Write :
7
NDER7
0
R/W
6
5
4
3
2
NDER6 NDER5 NDER4 NDER3 NDER2
0
0
0
0
0
R/W R/W R/W R/W R/W
1
0
NDER1 NDER0
0
0
R/W R/W
Pulse Output Enable/Disable
0 _{Pulse outputs PO7 to PO0 are disabled}
1 _{Pulse outputs PO7 to PO0 are enabled}
853