HD6432351 Datasheet, PDF (632/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

TDR
(1) Data write
(2) Transfer from
TDR to TSR
(3) Serial data output
Data 1
Data 1
Data 1
TSR
(shift register)
Data 1
; Data remains in TDR
Data 1
I/O signal line output
In case of normal transmission: TEND flag is set
In case of transmit error:
ERS flag is set
Steps (2) and (3) above are repeated until the TEND flag is set
Note: When the ERS flag is set, it should be cleared until transfer of the last bit (D7 in LSB-first
transmission, D0 in MSB-first transmission) of the next transfer data to be transmitted has
been completed.
Figure 14-5 Relation Between Transmit Operation and Internal Registers
I/O data
TXI
(TEND interrupt)
When GM = 0
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
12.5etu
Guard
time
When GM = 1
11.0etu
Legend
Ds
: Start bit
D0 to D7 : Data bits
Dp
: Parity bit
DE
: Error signal
Figure 14-6 TEND Flag Generation Timing in Transmission Operation
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