HD6432351 Datasheet, PDF (161/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

6.3 Overview of Bus Control
6.3.1 Area Partitioning
In advanced mode, the bus controller partitions the 16 Mbytes address space into eight areas, 0 to
7, in 2-Mbyte units, and performs bus control for external space in area units. In normal mode, it
controls a 64-kbyte address space comprising part of area 0. Figure 6-2 shows an outline of the
memory map.
Chip select signals (CS0 to CS7) can be output for each area.
H'000000
H'1FFFFF
H'200000
H'3FFFFF
H'400000
H'5FFFFF
H'600000
H'7FFFFF
H'800000
H'9FFFFF
H'A00000
H'BFFFFF
H'C00000
H'DFFFFF
H'E00000
H'FFFFFF
Area 0
(2Mbytes)
Area 1
(2Mbytes)
Area 2
(2Mbytes)
Area 3
(2Mbytes)
Area 4
(2Mbytes)
Area 5
(2Mbytes)
Area 6
(2Mbytes)
Area 7
(2Mbytes)
H'0000
H'FFFF
(1) Advanced mode
(2) Normal mode
Figure 6-2 Overview of Area Partitioning
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