HD6432351 Datasheet, PDF (510/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

11.1.2 Block Diagram
Figure 11-1 shows a block diagram of the PPG.
Compare match signals
Control logic
NDERH
PMR
NDERL
PCR
PO15
PO14
PO13
PO12
PO11
PO10
PO9
PO8
PO7
PO6
PO5
PO4
PO3
PO2
PO1
PO0
Pulse output
pins, group 3
Pulse output
pins, group 2
Pulse output
pins, group 1
Pulse output
pins, group 0
PODRH
PODRL
Legend
PMR : PPG output mode register
PCR : PPG output control register
NDERH : Next data enable register H
NDERL : Next data enable register L
NDRH : Next data register H
NDRL : Next data register L
PODRH : Output data register H
PODRL : Output data register L
NDRH
NDRL
Figure 11-1 Block Diagram of PPG
Internal
data bus
490