HD6432351 Datasheet, PDF (320/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

8.3.5 Normal Mode
In normal mode, one operation transfers one byte or one word of data.
From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a
CPU interrupt can be requested.
Table 8-5 lists the register information in normal mode and figure 8-6 shows memory mapping in
normal mode.
Table 8-5 Register Information in Normal Mode
Name
DTC source address register
DTC destination address register
DTC transfer count register A
DTC transfer count register B
Abbreviation
SAR
DAR
CRA
CRB
Function
Designates source address
Designates destination address
Designates transfer count
Not used
SAR
Transfer
DAR
Figure 8-6 Memory Mapping in Normal Mode
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