HD6432351 Datasheet, PDF (153/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Bit 3—DACK Timing Select (DDS): Selects the DMAC single address transfer bus timing for
the DRAM interface.
Bit 3
DDS
0
1
Description
When DMAC single address transfer is performed in DRAM space, full access is
always executed
DACK signal goes low from T_r or T₁ cycle
Burst access is possible when DMAC single address transfer is performed in DRAM
space
DACK signal goes low from T_c1 or T₂ cycle
(Initial value)
Bit 2—Reserved: Only 1 should be written to this bit.
Bit 1—Write Data Buffer Enable (WDBE): Selects whether or not the write buffer function is
used for an external write cycle or DMAC single address cycle.
Bit 1
WDBE
0
1
Description
Write data buffer function not used
Write data buffer function used
(Initial value)
Bit 0—WAIT Pin Enable (WAITE): Selects enabling or disabling of wait input by the WAIT
pin.
Bit 0
WAITE
0
1
Description
Wait input by WAIT pin disabled. WAIT pin can be used as I/O port.
Wait input by WAIT pin enabled
(Initial value)
133