HD6432351 Datasheet, PDF (347/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Table 9-3 Port 1 Pin Functions (cont)
Pin
Selection Method and Pin Functions
P1₂/PO10/TIOCC0/ The pin function is switched as shown below according to the combination of
TCLKA
the TPU channel 0 setting by bits MD3 to MD0 in TMDR0, bits IOC3 to IOC0 in
TIOR0L, bits CCLR2 to CCLR0 in TCR0, bits TPSC2 to TPSC0 in TCR0 to
TCR5, bit NDER10 in NDERH, and bit P12DDR.
TPU Channel
0 Setting
Table Below (1)
Table Below (2)
P12DDR
—
0
1
1
NDER10
—
—
0
1
Pin function
TIOCC0 output
P1₂
input
P1₂
output
PO10
output
TIOCC0 input *¹
TCLKA input *²
Notes: 1. TIOCC0 input when MD3 to MD0 = B'0000, and IOC3 to IOC0 =
B'10xx.
2. TCLKA input when the setting for TCR0 to TCR5 is: TPSC2 to
TPSC0 = B'100;
TCLKA input when channels 1 and 5 are set to phase counting
mode.
TPU Channel
0 Setting
MD3 to MD0
IOC3 to IOC0
CCLR2 to
CCLR0
Output
function
(2)
(1)
(2)
B'0000
B'001x
B'0000
B'0100
B'1xxx
B'0001 to
B'0011
B'0101 to
B'0111
B'xx00
—
—
—
—
Output
—
compare
output
(1)
(1)
(2)
B'0010
B'0011
Other than B'xx00
—
PWM
mode 1
output*³
Other
than
B'101
B'101
PWM
—
mode 2
output
x: Don’t care
Note: 3. TIOCD0 output is disabled.
When BFA = 1 or BFB = 1 in TMDR0, output is disabled and setting
(2) applies.
327