HD6432351 Datasheet, PDF (478/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

TCNT value
TGRA
Counter cleared by
TGRA compare match
TGRB
H'0000
Time
TIOCA
Figure 10-25 Example of PWM Mode Operation (1)
Figure 10-26 shows an example of PWM mode 2 operation.
In this example, synchronous operation is designated for channels 0 and 1, TGR1B compare match
is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output
value of the other TGR registers (TGR0A to TGR0D, TGR1A), to output a 5-phase PWM
waveform.
In this case, the value set in TGR1B is used as the cycle, and the values set in the other TGRs as
the duty.
TCNT value
TGR1B
TGR1A
TGR0D
TGR0C
TGR0B
TGR0A
H'0000
Counter cleared by TGR1B
compare match
TIOCA0
TIOCB0
TIOCC0
TIOCD0
TIOCA1
Figure 10-26 Example of PWM Mode Operation (2)
Time
458