HD6432351 Datasheet, PDF (884/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

PDDR—Port D Data Register
H'FF6C
Port D
[H8S/2351 Only]
Bit
:
Initial value :
Read/Write :
7
PD7DR
0
R/W
6
5
4
3
2
PD6DR PD5DR PD4DR PD3DR PD2DR
0
0
0
0
0
R/W R/W R/W R/W R/W
1
0
PD1DR PD0DR
0
0
R/W R/W
Stores output data for port D pins (PD₇ to PD₀)
PEDR—Port E Data Register
H'FF6D
Port E
Bit
:
Initial value :
Read/Write :
7
PE7DR
0
R/W
6
5
PE6DR PE5DR
0
0
R/W R/W
4
3
PE4DR PE3DR
0
0
R/W R/W
2
PE2DR
0
R/W
1
0
PE1DR PE0DR
0
0
R/W R/W
Stores output data for port E pins (PE₇ to PE₀)
PFDR—Port F Data Register
H'FF6E
Port F
Bit
:
Initial value :
Read/Write :
7
PF7DR
0
R/W
6
PF6DR
0
R/W
5
PF5DR
0
R/W
4
PF4DR
0
R/W
3
PF3DR
0
R/W
2
PF2DR
0
R/W
1
0
PF1DR PF0DR
0
0
R/W R/W
Stores output data for port F pins (PF₇ to PF₀)
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