HD6432351 Datasheet, PDF (200/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

(2) Write after Read
If an external write occurs after an external read while the ICIS0 bit in BCRH is set to 1, an idle
cycle is inserted at the start of the write cycle.
Figure 6-32 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an
idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and
the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented.
ø
Address bus
CS (area A)
CS (area B)
RD
HWR
Data bus
Bus cycle A Bus cycle B
T₁ T₂ T₃ T₁ T₂
ø
Address bus
CS (area A)
CS (area B)
RD
HWR
Data bus
Bus cycle A
T₁ T₂ T₃
Bus cycle B
T_I T₁ T₂
Long output
floating time
(a) Idle cycle not inserted
(ICIS1 = 0)
Data
collision
(b) Idle cycle inserted
(Initial value ICIS1 = 1)
Figure 6-32 Example of Idle Cycle Operation (2)
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