HD6432351 Datasheet, PDF (15/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

10.4.6 PWM Modes ......................................................................................................... 455
10.4.7 Phase Counting Mode ........................................................................................... 460
10.5 Interrupts ............................................................................................................................ 467
10.5.1 Interrupt Sources and Priorities ............................................................................ 467
10.5.2 DTC/DMAC Activation........................................................................................ 469
10.5.3 A/D Converter Activation..................................................................................... 469
10.6 Operation Timing ............................................................................................................... 470
10.6.1 Input/Output Timing ............................................................................................. 470
10.6.2 Interrupt Signal Timing ........................................................................................ 474
10.7 Usage Notes ....................................................................................................................... 478
Section 11 Programmable Pulse Generator (PPG) ..................................................... 489
11.1 Overview............................................................................................................................ 489
11.1.1 Features ................................................................................................................. 489
11.1.2 Block Diagram...................................................................................................... 490
11.1.3 Pin Configuration.................................................................................................. 491
11.1.4 Registers................................................................................................................ 492
11.2 Register Descriptions ......................................................................................................... 493
11.2.1 Next Data Enable Registers H and L (NDERH, NDERL) ................................... 493
11.2.2 Output Data Registers H and L (PODRH, PODRL) ............................................ 494
11.2.3 Next Data Registers H and L (NDRH, NDRL) .................................................... 495
11.2.4 Notes on NDR Access .......................................................................................... 495
11.2.5 PPG Output Control Register (PCR) .................................................................... 497
11.2.6 PPG Output Mode Register (PMR) ...................................................................... 499
11.2.7 Port 1 Data Direction Register (P1DDR).............................................................. 502
11.2.8 Port 2 Data Direction Register (P2DDR).............................................................. 502
11.2.9 Module Stop Control Register (MSTPCR)........................................................... 503
11.3 Operation............................................................................................................................ 504
11.3.1 Overview............................................................................................................... 504
11.3.2 Output Timing ...................................................................................................... 505
11.3.3 Normal Pulse Output ............................................................................................ 506
11.3.4 Non-Overlapping Pulse Output ............................................................................ 508
11.3.5 Inverted Pulse Output ........................................................................................... 511
11.3.6 Pulse Output Triggered by Input Capture............................................................. 512
11.4 Usage Notes ....................................................................................................................... 513
Section 12 Watchdog Timer.............................................................................................. 515
12.1 Overview............................................................................................................................ 515
12.1.1 Features ................................................................................................................. 515
12.1.2 Block Diagram...................................................................................................... 516
12.1.3 Pin Configuration.................................................................................................. 517
12.1.4 Register Configuration.......................................................................................... 517
12.2 Register Descriptions ......................................................................................................... 518
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