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HD6432351 Datasheet, PDF (670/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise
DADR0
write cycle
DACR
write cycle
DADR0
write cycle
DACR
write cycle
ø
Address
DADR0
DAOE0
Conversion data 1
Conversion data 2
DA0
High-impedance state
tDCONV
Conversion
result 1
Conversion
result 2
tDCONV
Legend
tDCONV: D/A conversion time
Figure 16-2 Example of D/A Converter Operation
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