HD6432351 Datasheet, PDF (275/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

7.5.9 Basic DMAC Bus Cycles
An example of the basic DMAC bus cycle timing is shown in figure 7-18. In this example, word-
size transfer is performed from 16-bit , 2-state access space to 8-bit, 3-state access space. When
the bus is transferred from the CPU to the DMAC, a source address read and destination address
write are performed. The bus is not released in response to another bus request, etc., between
these read and write operations. As with CPU cycles, DMA cycles conform to the bus controller
settings.
CPU cycle
DMAC cycle (1-word transfer)
CPU cycle
ø
Address bus
T₁ T₂ T₁ T₂ T₃ T₁ T₂ T₃
Source
address
Destination address
RD
HWR
LWR
Figure 7-18 Example of DMA Transfer Bus Timing
The address is not output to the external address bus in an access to on-chip memory or an internal
I/O register.
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