HD6432351 Datasheet, PDF (687/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

20.2 Register Descriptions
20.2.1 Standby Control Register (SBYCR)
Bit
:
7
6
5
4
3
2
SSBY STS2 STS1 STS0 OPE
—
Initial value :
0
0
0
0
1
0
R/W
:
R/W
R/W
R/W
R/W
R/W
—
1
0
—
—
0
0
—
R/W
SBYCR is an 8-bit readable/writable register that performs software standby mode control.
SBYCR is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Software Standby (SSBY): Specifies a transition to software standby mode. Remains set
to 1 when software standby mode is released by an external interrupt, and a transition is made to
normal operation. The SSBY bit should be cleared by writing 0 to it.
Bit 7
SSBY
0
1
Description
Transition to sleep mode after execution of SLEEP instruction
(Initial value)
Transition to software standby mode after execution of SLEEP instruction
Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the time the MCU
waits for the clock to stabilize when software standby mode is cleared by an external interrupt.
With crystal oscillation, refer to table 20-4 and make a selection according to the operating
frequency so that the standby time is at least 8 ms (the oscillation stabilization time). With an
external clock, any selection can be made.
Bit 6
STS2
0
1
Bit 5
STS1
0
1
0
1
Bit 4
STS0
0
1
0
1
0
1
0
1
Description
Standby time = 8192 states
Standby time = 16384 states
Standby time = 32768 states
Standby time = 65536 states
Standby time = 131072 states
Standby time = 262144 states
Reserved
Standby time = 16 states
(Initial value)
667