HD6432351 Datasheet, PDF (19/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

20.2.3 Module Stop Control Register (MSTPCR)........................................................... 669
20.3 Medium-Speed Mode......................................................................................................... 670
20.4 Sleep Mode ........................................................................................................................ 671
20.5 Module Stop Mode ............................................................................................................ 671
20.5.1 Module Stop Mode ............................................................................................... 671
20.5.2 Usage Notes .......................................................................................................... 672
20.6 Software Standby Mode..................................................................................................... 673
20.6.1 Software Standby Mode........................................................................................ 673
20.6.2 Clearing Software Standby Mode......................................................................... 673
20.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode ... 674
20.6.4 Software Standby Mode Application Example .................................................... 674
20.6.5 Usage Notes .......................................................................................................... 675
20.7 Hardware Standby Mode ................................................................................................... 676
20.7.1 Hardware Standby Mode ...................................................................................... 676
20.7.2 Hardware Standby Mode Timing ......................................................................... 676
20.8 ø Clock Output Disabling Function ................................................................................... 677
Section 21 Electrical Characteristics .............................................................................. 679
21.1 Absolute Maximum Ratings .............................................................................................. 679
21.2 DC Characteristics ............................................................................................................. 680
21.3 AC Characteristics ............................................................................................................. 685
21.3.1 Clock Timing ........................................................................................................ 686
21.3.2 Control Signal Timing .......................................................................................... 688
21.3.3 Bus Timing ........................................................................................................... 690
21.3.4 DMAC Timing...................................................................................................... 700
21.3.5 Timing of On-Chip Supporting Modules.............................................................. 704
21.4 A/D Conversion Characteristics ........................................................................................ 709
21.5 D/A Convervion Characteristics ........................................................................................ 710
21.6 Usage Note ......................................................................................................................... 710
Appendix A Instruction Set............................................................................................... 711
A.1 Instruction List ................................................................................................................... 711
A.2 Instruction Codes ............................................................................................................... 735
A.3 Operation Code Map.......................................................................................................... 750
A.4 Number of States Required for Instruction Execution....................................................... 754
A.5 Bus States During Instruction Execution ........................................................................... 765
A.6 Condition Code Modification ............................................................................................ 779
Appendix B Internal I/O Register ................................................................................... 785
B.1 Addresses ........................................................................................................................... 785
B.2 Functions............................................................................................................................ 794
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