HD6432351 Datasheet, PDF (193/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

T_Rp
ø
T_Rr
T_Rc1
T_Rw
T_Rc2
CSn (RAS)
CAS, LCAS
Figure 6-26 CBR Refresh Timing (When RCW = 1, RLW1 = 0, RLW0 = 1)
(2) Self-Refreshing
A self-refresh mode (battery backup mode) is provided for DRAM as a kind of standby mode. In
this mode, refresh timing and refresh addresses are generated within the DRAM.
To select self-refreshing, set the RFSHE bit and RMODE bit in DRAMCR to 1. Then, when a
SLEEP instruction is executed to enter software standby mode, the CAS and RAS signals are
output and DRAM enters self-refresh mode, as shown in figure 6-27.
When software standby mode is exited, the RMODE bit is cleared to 0 and self-refresh mode is
cleared.
When switching to software standby mode, if there is a CBR refresh request, CBR refreshing is
executed before self-refresh mode is entered.
T_Rp
T_Rcr
ø
Software
standby
T_Rc3
CSn (RAS)
CAS, LCAS
HWR (WE)
High
Note: n = 2 to 5
Figure 6-27 Self-Refresh Timing (When CW2 = 1, or CW2 = 0 and LCASS = 0)
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