HD6432351 Datasheet, PDF (977/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Table D-1 I/O Port States in Each Processing State (H8S/2351) (cont)
MCU
Port Name Operating
Pin Name Mode
PF₂/LCAS/
WAIT/
BREQO
1, 2, 4 to 6
3, 7
PF₁/BACK 1, 2, 4 to 6
3, 7
PF₀/BREQ 1, 2, 4 to 6
PG₄/CS0
3, 7
1, 4, 5
2, 6
Power-
On
Manual
Reset Reset
Hardware Software
Standby Standby
Mode Mode
Bus
Release
State
Program
Execution
State
Sleep Mode
T
[BREQOE + T
WAITE +
LCASE = 0]
kept
[BREQOE = 1]
BREQO
[WAITE = 1]
T
[LCASE = 1]
H*
[BREQOE +
WAITE +
LCASE = 0]
kept
[BREQOE = 1]
kept
[WAITE = 1]
T
[LCASE = 1,
OPE = 0]
T
[LCASE = 1,
OPE = 1]
LCAS
[BREQOE + [BREQOE +
WAITE +
WAITE +
LCASE = 0] LCASE= 0]
kept
I/O port
[BREQOE = 1] [BREQOE = 1]
BREQO
BREQO
[WAITE = 1] [WAITE = 1]
T
WAIT
[LCASE = 1] [LCASE = 1]
T
LCAS
T
kept
T
kept
kept
I/O port
T
[BRLE = 0] T
kept
[BRLE = 1]
BACK
[BRLE = 0]
L
kept
[BRLE = 1]
H
[BRLE = 0]
I/O port
[BRLE = 1]
BACK
T
kept
T
kept
kept
I/O port
T
[BRLE = 0] T
kept
[BRLE = 1]
BREQ
[BRLE = 0]
T
kept
[BRLE = 1]
T
[BRLE = 0]
I/O port
[BRLE = 1]
BREQ
T
kept
T
kept
kept
I/O port
H
[DDR = 0] T
T
T
[DDR = 1]
H*
[DDR · OPE = 0] T
T
[DDR · OPE = 1]
H
[DDR = 0]
Input port
[DDR = 1]
CS0
3, 7
T
PG₃/CS1 1 to 3, 7
T
PG₂/CS2 _{4 to 6}
T
PG₁/CS3
kept
T
kept
T
[DDR = 0] T
T
[DDR = 1]
H*
kept
kept
kept
kept
[DDR · OPE = 0] T
T
[DDR · OPE = 1]
H
I/O port
I/O port
[DDR = 0]
Input port
[DDR = 1]
CS1 to CS3
957