HD6432351 Datasheet, PDF (151/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Bit 4—Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycles for the burst ROM
interface.
Bit 4
BRSTS1
0
1
Description
Burst cycle comprises 1 state
Burst cycle comprises 2 states
(Initial value)
Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a
burst ROM interface burst access.
Bit 3
BRSTS0
0
1
Description
Max. 4 words in burst access
Max. 8 words in burst access
(Initial value)
Bits 2 to 0—RAM Type Select (RMTS2 to RMTS0): These bits select the memory interface for
areas 2 to 5 in advanced mode.
When DRAM space is selected, the relevant area is designated as DRAM interface.
Bit 2
RMTS2
Bit 1
RMTS1
Bit 0
RMTS0
Description
Area 5
Area 4
Area 3
Area 2
0
0
0
Normal space
1
Normal space
DRAM space
1
0
Normal space
DRAM space
1
DRAM space
1
—
—
—
Note: When areas selected in DRAM space are all 8-bit space, the PF₂ pin can be used as an I/O
port, BREQO, or WAIT.
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