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| HD6432351 Datasheet, PDF (173/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise | |||
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Bus cycle
T1
T2
ø
Address bus
CSn
AS
RD
Read
D15 to D8
Invalid
D7 to D0
HWR
High
Valid
Write
LWR
D15 to D8
High impedance
D7 to D0
Note: n = 0 to 7
Valid
Figure 6-9 Bus Timing for 16-Bit 2-State Access Space (2) (Odd Address Byte Access)
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