HD6432351 Datasheet, PDF (157/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

6.2.7 DRAM Control Register (DRAMCR)
Bit
:
Initial value :
R/W
:
7
RFSHE
0
R/W
6
RCW
0
R/W
5
RMODE
0
R/W
4
CMF
0
R/W
3
CMIE
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
DRAMCR is an 8-bit readable/writable register that selects the DRAM refresh mode and refresh
counter clock, and controls the refresh timer.
DRAMCR is initialized to H'00 by a power-on reset and in hardware standby mode. It is not
initialized by a manual reset or in software standby mode.
Bit 7—Refresh Control (RFSHE): Selects whether or not refresh control is performed. When
refresh control is not performed, the refresh timer can be used as an interval timer. Refresh control
is not performed in normal mode.
Bit 7
RFSHE
0
1
Description
Refresh control is not performed
Refresh control is performed
(Initial value)
Bit 6—RAS-CAS Wait (RCW): Controls wait state insertion in DRAM interface CAS-before-
RAS refreshing.
Bit 6
RCW
0
1
Description
Wait state insertion in CAS-before-RAS refreshing disabled
RAS falls in T_Rr cycle
One wait state inserted in CAS-before-RAS refreshing
RAS falls in T_Rc1 cycle
(Initial value)
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