HD6432351 Datasheet, PDF (488/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Table 10-13 TPU Interrupts
Interrupt
Channel Source Description
DMAC
DTC
Activation Activation Priority
0
TGI0A TGR0A input capture/compare match Possible Possible
High
TGI0B TGR0B input capture/compare match Not possible Possible
TGI0C TGR0C input capture/compare match Not possible Possible
TGI0D TGR0D input capture/compare match Not possible Possible
TCI0V TCNT0 overflow
Not possible Not possible
1
TGI1A TGR1A input capture/compare match Possible Possible
TGI1B TGR1B input capture/compare match Not possible Possible
TCI1V TCNT1 overflow
Not possible Not possible
TCI1U TCNT1 underflow
Not possible Not possible
2
TGI2A TGR2A input capture/compare match Possible Possible
TGI2B TGR2B input capture/compare match Not possible Possible
TCI2V TCNT2 overflow
Not possible Not possible
TCI2U TCNT2 underflow
Not possible Not possible
3
TGI3A TGR3A input capture/compare match Possible Possible
TGI3B TGR3B input capture/compare match Not possible Possible
TGI3C TGR3C input capture/compare match Not possible Possible
TGI3D TGR3D input capture/compare match Not possible Possible
TCI3V TCNT3 overflow
Not possible Not possible
4
TGI4A TGR4A input capture/compare match Possible Possible
TGI4B TGR4B input capture/compare match Not possible Possible
TCI4V TCNT4 overflow
Not possible Not possible
TCI4U TCNT4 underflow
Not possible Not possible
5
TGI5A TGR5A input capture/compare match Possible Possible
TGI5B TGR5B input capture/compare match Not possible Possible
TCI5V TCNT5 overflow
Not possible Not possible
TCI5U TCNT5 underflow
Not possible Not possible Low
Note: This table shows the initial state immediately after a reset. The relative channel priorities
can be changed by the interrupt controller.
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