HD6432351 Datasheet, PDF (401/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

9.12.2 Register Configuration
Table 9-21 shows the port E register configuration.
Table 9-21 Port E Registers
Name
Abbreviation R/W
Port E data direction register
PEDDR
W
Port E data register
PEDR
R/W
Port E register
PORTE
R
Port E MOS pull-up control register*² PEPCR
R/W
Notes: 1. Lower 16 bits of the address.
2. Only applies to the H8S/2351.
Initial Value
H'00
H'00
Undefined
H'00
Address*¹
H'FEBD
H'FF6D
H'FF5D
H'FF74
Port E Data Direction Register (PEDDR)
Bit
:
Initial value :
R/W
:
7
6
5
4
3
2
1
0
PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR
0
0
0
0
0
0
0
0
W
W
W
W
W
W
W
W
PEDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port E. PEDDR cannot be read; if it is, an undefined value will be read.
PEDDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its
prior state after a manual reset, and in software standby mode.
• Modes 1, 4, 5 [H8S/2350]; modes 1, 2, 4, 5, and 6 [H8S/2351]
When 8-bit bus mode has been selected, port E pins function as I/O ports. Setting a PEDDR bit
to 1 makes the corresponding port E pin an output port, while clearing the bit to 0 makes the
pin an input port.
When 16-bit bus mode has been selected, the input/output direction specification by PEDDR is
ignored, and port E is designated for data I/O.
For details of 8-bit and 16-bit bus modes, see section 6, Bus Controller.
• Modes 3 and 7 [H8S/2351 only]
Setting a PEDDR bit to 1 makes the corresponding port E pin an output port, while clearing the
bit to 0 makes the pin an input port.
381