HD6432351 Datasheet, PDF (607/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Table 13-12 SCI Interrupt Sources
Interrupt
Channel Source Description
DTC
DMAC
Activation Activation Priority*
0
ERI
Interrupt due to receive error
Not
Not
High
(ORER, FER, or PER)
possible possible
RXI
Interrupt due to receive data full
Possible Possible
state (RDRF)
TXI
Interrupt due to transmit data empty Possible Possible
state (TDRE)
TEI
Interrupt due to transmission end Not
Not
(TEND)
possible possible
1
ERI
Interrupt due to receive error
Not
Not
(ORER, FER, or PER)
possible possible
RXI
Interrupt due to receive data full
Possible Possible
state (RDRF)
TXI
Interrupt due to transmit data empty Possible Possible
state (TDRE)
TEI
Interrupt due to transmission end Not
Not
(TEND)
possible possible
Low
Note: * This table shows the initial state immediately after a reset. Relative priorities among
channels can be changed by means of the interrupt controller.
A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. The
TEND flag is cleared at the same time as the TDRE flag. Consequently, if a TEI interrupt and a
TXI interrupt are requested simultaneously, the TXI interrupt may have priority for acceptance,
with the result that the TDRE and TEND flags are cleared. Note that the TEI interrupt will not be
accepted in this case.
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