HD6432351 Datasheet, PDF (24/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Table 1-1 Overview (cont)
Item
Power-down state
Operating modes
Clock pulse
generator
Packages
Product lineup
Specification
• Medium-speed mode
• Sleep mode
• Module stop mode
• Software standby mode
• Hardware standby mode
Seven MCU operating modes
CPU
Operating
Mode Mode
Description
1 Normal On-chip ROM disabled
expansion mode
2*
On-chip ROM enabled
expansion mode
3*
Single-chip mode
4 Advanced On-chip ROM disabled
expansion mode
5
On-chip ROM disabled
expansion mode
6*
On-chip ROM enabled
expansion mode
7*
Single-chip mode
Note: * Only applies to the H8S/2351.
• Built-in duty correction circuit
External Data Bus
On-Chip _{Initial Maximum}
ROM _{Value Value}
Disabled 8 bits 16 bits
Enabled 8 bits 16 bits
Enabled —
Disabled 16 bits 16 bits
Disabled 8 bits 16 bits
Enabled 8 bits 16 bits
Enabled —
• 120-pin plastic TQFP (TFP-120)
• 128-pin plastic QFP (FP-128)
Model Name
ROMless
Version
Mask ROM
Version
—
HD6432351
HD6412350
—
ROM/RAM
(Bytes)
64 k/2 k
—/2 k
Packages
TFP-120
FP-128
TFP-120
FP-128
4