HD6432351 Datasheet, PDF (169/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

6.4.3 Valid Strobes
Table 6-4 shows the data buses used and valid strobes for the access spaces.
In a read, the RD signal is valid without discrimination between the upper and lower halves of the
data bus.
In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the
lower half.
Table 6-4 Data Buses Used and Valid Strobes
Area
8-bit access
space
Access Read/
Valid
Size Write Address Strobe
Byte Read —
RD
Write —
HWR
Upper Data Bus
(D₁₅ to D₈)
Valid
16-bit access Byte Read Even
RD
space
Odd
Valid
Invalid
Write Even
HWR
Valid
Odd
LWR
Hi-Z
Word Read —
RD
Valid
Write —
HWR, LWR Valid
Note: Hi-Z: High impedance
Invalid: Input state; input value is ignored.
Lower data bus
(D₇ to D₀)
Invalid
Hi-Z
Invalid
Valid
Hi-Z
Valid
Valid
Valid
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