HD6432351 Datasheet, PDF (535/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Section 12 Watchdog Timer
12.1 Overview
The H8S/2350 Series has a single-channel on-chip watchdog timer (WDT) for monitoring system
operation. The WDT outputs an overflow signal (WDTOVF) if a system crash prevents the CPU
from writing to the timer counter, allowing it to overflow. At the same time, the WDT can also
generate an internal reset signal for the H8S/2350 Series.
When this watchdog function is not needed, the WDT can be used as an interval timer. In interval
timer operation, an interval timer interrupt is generated each time the counter overflows.
12.1.1 Features
WDT features are listed below.
• Switchable between watchdog timer mode and interval timer mode
• WDTOVF output when in watchdog timer mode
If the counter overflows, the WDT outputs WDTOVF. It is possible to select whether or not
the entire H8S/2350 Series is reset at the same time. This internal reset can be a power-on
reset or a manual reset.
• Interrupt generation when in interval timer mode
If the counter overflows, the WDT generates an interval timer interrupt.
• Choice of eight counter clock sources.
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