HD6432351 Datasheet, PDF (851/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

ETCR0B—Transfer Count Register 0B
H'FEEE
DMAC
Bit
: _{15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0}
ETCR0B :
Initial value : _{* * * * * * * * * * * * * * * *}
Read/Write : _{R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W}
Sequential
mode and
idle mode
Transfer counter
Repeat mode
Transfer number storage register
Block transfer
mode
Block transfer counter
Note: Not used in normal mode.
Transfer counter
* : Undefined
MAR1AH—Memory Address Register 1AH
MAR1AL—Memory Address Register 1AL
H'FEF0
H'FEF2
DMAC
DMAC
Bit
: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MAR1AH : — — — — — — — —
Initial value : 0 0 0 0 0 0 0 0 * * * * * * * *
Read/Write : — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W
Bit
: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MAR1AL :
Initial value : * * * * * * * * * * * * * * * *
Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
* : Undefined
In short address mode: Specifies transfer source/transfer destination address
In full address mode: Specifies transfer source address
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