HD6432351 Datasheet, PDF (672/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

17.1.2 Register Configuration
The on-chip RAM is controlled by SYSCR. Table 17-1 shows the address and initial value of
SYSCR.
Table 17-1 RAM Register
Name
Abbreviation R/W
System control register
SYSCR
R/W
Note: * Lower 16 bits of the address.
Initial Value
H'01
Address*
H'FF39
17.2 Register Descriptions
17.2.1 System Control Register (SYSCR)
Bit
:
7
—
Initial value :
0
R/W
: R/W
6
5
4
3
2
— INTM1 INTM0 NMIEG —
0
0
0
0
0
—
R/W R/W R/W
—
1
0
— RAME
0
1
R/W R/W
The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. For details of other bits in
SYSCR, see section 3.2.2, System Control Register (SYSCR).
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized when the reset state is released. It is not initialized in software standby mode.
Bit 0
RAME
0
1
Description
On-chip RAM is disabled
On-chip RAM is enabled
(Initial value)
652