HD6432351 Datasheet, PDF (912/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

TCNT—Timer Counter
H'FFBC (W) H'FFBD (R)
WDT
Bit
:7
6
5
4
3
2
1
0
Initial value : 0
Read/Write : R/W
0
0
R/W R/W
0
0
0
R/W R/W R/W
0
0
R/W R/W
RSTCSR—Reset Control/Status Register
Bit
:
Initial value :
Read/Write :
7
WOVF
0
R/(W)*
6
RSTE
0
R/W
5
RSTS
0
R/W
H'FFBE (W) H'FFBF (R)
4
3
2
1
—
—
—
—
1
1
1
1
—
—
—
—
WDT
0
—
1
—
Reset Select
0 Power-on reset
1 Manual reset
Reset Enable
0 Reset signal is not generated if TCNT overflows*
1 Reset signal is generated if TCNT overflows
Note: * The modules H8S/2350 Series are not reset, but TCNT
and TCSR in WDT are reset.
Watchdog Timer Overflow Flag
0 [Clearing condition]
Cleared by reading TCSR when WOVF = 1, then writing 0 to WOVF
1 [Setting condition]
Set when TCNT overflows (changed from H'FF to H'00) during
watchdog timer operation
Note: * Can only be written with 0 for flag clearing.
The method for writing to RSTCSR is different from that for general registers to prevent
accidental overwriting. For details see section 12.2.4, Notes on Register Access.
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