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HD6432351 Datasheet, PDF (828/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise | |||
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TSR4âTimer Status Register 4
H'FE95
TPU4
Bit
:
Initial value :
Read/Write :
7
TCFD
1
R
6
5
4
3
â
TCFU TCFV
â
1
0
0
0
â R/(W)* R/(W)* â
2
1
0
â
TGFB TGFA
0
0
0
â R/(W)* R/(W)*
Input Capture/Output Compare Flag A
0 [Clearing condition]
⢠When DTC is activated by TGIA interrupt while
DISEL bit of MRB in DTC is 0
⢠When DMAC is activated by TGIA interrupt while
DTA bit of DMABCR in DMAC is 1
⢠When 0 is written to TGFA after reading TGFA = 1
1 [Setting conditions]
⢠When TCNT = TGRA while TGRA is functioning
as output compare register
⢠When TCNT value is transferred to TGRA by
input capture signal while TGRA is functioning
as input capture register
Input Capture/Output Compare Flag B
0 [Clearing condition]
⢠When DTC is activated by TGIB interrupt while DISEL
bit of MRB in DTC is 0
⢠When 0 is written to TGFB after reading TGFB = 1
1 [Setting conditions]
⢠When TCNT = TGRB while TGRB is functioning as
output compare register
⢠When TCNT value is transferred to TGRB by input
capture signal while TGRB is functioning as input
capture register
Overflow Flag
0 [Clearing condition]
When 0 is written to TCFV after reading TCFV = 1
1 [Setting conditions]
When the TCNT value overflows (changes from H'FFFF to H'0000 )
Underflow Flag
0 [Clearing condition]
When 0 is written to TCFU after reading TCFU = 1
1 [Setting conditions]
When the TCNT value underflows (changes from H'0000 to H'FFFF)
Count Direction Flag
0 TCNT counts down
1 TCNT counts up
Note: * Can only be written with 0 for flag clearing.
808
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