HD6432351 Datasheet, PDF (426/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

10.2 Register Descriptions
10.2.1 Timer Control Register (TCR)
Channel 0: TCR0
Channel 3: TCR3
Bit
:
Initial value :
R/W
:
7
CCLR2
0
R/W
6
CCLR1
0
R/W
5
CCLR0
0
R/W
4
3
CKEG1 CKEG0
0
0
R/W R/W
2
TPSC2
0
R/W
1
TPSC1
0
R/W
0
TPSC0
0
R/W
Channel 1: TCR1
Channel 2: TCR2
Channel 4: TCR4
Channel 5: TCR5
Bit
:
7
6
5
4
3
2
1
0
— CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0
Initial value :
0
0
0
0
0
0
0
0
R/W
:—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
The TCR registers are 8-bit registers that control the TCNT channels. The TPU has six TCR
registers, one for each of channels 0 to 5. The TCR registers are initialized to H'00 by a reset, and
in hardware standby mode.
TCR register settings should be made only when TCNT operation is stopped.
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