HD6432351 Datasheet, PDF (711/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Table 21-6 Bus Timing (cont)
Condition A: V_CC = 2.7 to 5.5 V, AV_CC = 2.7 to 5.5 V, V_ref = 2.7 V to AV_CC,
V_SS = AV_SS = 0 V, ø = 2 to 10 MHz, T_a = –20 to +75°C (regular specifications),
T_a = –40 to +85°C (wide-range specifications)
Condition B: V_CC = 5.0 V ± 10%, AV_CC = 5.0 V ± 10%, V_ref = 4.5 V to AV_CC,
V_SS = AV_SS = 0 V, ø= 2 to 20 MHz, T_a = –20 to +75°C (regular specifications),
T_a = –40 to +85°C (wide-range specifications)
Item
Read data access
time 4
Read data access
time 5
WR delay time 1
WR delay time 2
WR pulse width 1
Symbol
t _ACC4
t _ACC5
t _WRD1
t _WRD2
t _WSW1
WR pulse width 2
t _WSW2
Write data delay time t _WDD
Write data setup time t _WDS
Write data hold time t _WDH
WR setup time
t _WCS
WR hold time
t _WCH
CAS setup time
t _CSR
WAIT setup time
WAIT hold time
BREQ setup time
BACK delay time
Bus-floating time
BREQO delay time
t _WTS
t _WTH
t _BRQS
t _BACD
t _BZD
t _BRQOD
Condition A
Condition B
Min Max Min Max Unit
—
2.5 × —
2.5 × ns
t _cyc – 50
t _cyc – 25
—
3.0 × —
3.0 × ns
t _cyc – 50
t _cyc – 25
—
40
—
20
ns
—
40
—
20
ns
1.0 × —
1.0 × —
ns
t _cyc – 40
t _cyc – 20
1.5 × —
1.5 × —
ns
t _cyc – 40
t _cyc – 20
—
60
—
30
ns
0.5 × —
0.5 × —
ns
t _cyc – 40
t _cyc – 20
0.5 × —
0.5 × —
ns
t _cyc – 20
t _cyc – 10
0.5 × —
0.5 × —
ns
t _cyc – 20
t _cyc – 10
0.5 × —
0.5 × —
ns
t _cyc – 20
t _cyc – 10
0.5 × —
0.5 × —
ns
t _cyc – 20
t _cyc – 10
60
—
30
—
ns
10
—
5
—
ns
60
—
30
—
ns
—
30
—
15
ns
—
100
—
50
ns
—
60
—
30
ns
Test Conditions
Figure 21-8 to
Figure 21-15
Figure 21-12
Figure 21-10
Figure 21-16
Figure 21-17
691