HD6432351 Datasheet, PDF (500/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Contention between TCNT Write and Increment Operations: If incrementing occurs in the T2
state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented.
Figure 10-50 shows the timing in this case.
ø
Address
Write signal
TCNT input
clock
TCNT
TCNT write cycle
T1
T2
TCNT address
N
M
TCNT write data
Figure 10-50 Contention between TCNT Write and Increment Operations
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