HD6432351 Datasheet, PDF (237/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

7.3.5 DMA Band Control Register (DMABCR)
Bit
:
DMABCRH :
Initial value :
R/W
:
15
14
13
FAE1 FAE0
—
0
0
0
R/W
R/W
R/W
12
11
10
9
8
—
DTA1
—
DTA0
—
0
0
0
0
0
R/W R/W R/W R/W R/W
Bit
:
DMABCRL :
Initial value :
R/W
:
7
DTME1
0
R/W
6
DTE1
0
R/W
5
DTME0
0
R/W
4
DTE0
0
R/W
3
2
1
0
DTIE1B DTIE1A DTIE0B DTIE0A
0
0
0
0
R/W R/W R/W R/W
DMABCR is a 16-bit readable/writable register that controls the operation of each DMAC
channel.
DMABCR is initialized to H'0000 by a reset, and in standby mode.
Bit 15—Full Address Enable 1 (FAE1): Specifies whether channel 1 is to be used in short
address mode or full address mode.
In full address mode, channels 1A and 1B are used together as a single channel.
Bit 15
FAE1
0
1
Description
Short address mode
Full address mode
(Initial value)
Bit 14—Full Address Enable 0 (FAE0): Specifies whether channel 0 is to be used in short
address mode or full address mode.
In full address mode, channels 0A and 0B are used together as a single channel.
Bit 14
FAE0
0
1
Description
Short address mode
Full address mode
(Initial value)
217