HD6432351 Datasheet, PDF (181/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

6.5.4 Data Bus
If the bit in ABWCR corresponding to an area designated as DRAM space is set to 1, that area is
designated as 8-bit DRAM space; if the bit is cleared to 0, the area is designated as 16-bit DRAM
space. In 16-bit DRAM space, × 16-bit configuration DRAM can be connected directly.
In 8-bit DRAM space the upper half of the data bus, D₁₅ to D₈, is enabled, while in 16-bit DRAM
space both the upper and lower halves of the data bus, D₁₅ to D₀, are enabled.
Access sizes and data alignment are the same as for the basic bus interface: see section 6.4.2, Data
Size and Data Alignment.
6.5.5 Pins Used for DRAM Interface
Table 6-7 shows the pins used for DRAM interfacing and their functions.
Table 6-7 DRAM Interface Pins
Pin
HWR
LCAS
CS2
CS3
CS4
CS5
CAS
WAIT
A₁₂ to A₀
D₁₅ to D₀
With DRAM
Setting
WE
LCAS
RAS2
RAS3
RAS4
RAS5
UCAS
WAIT
A₁₂ to A₀
D₁₅ to D₀
Name
I/O
Function
Write enable
Output When 2-CAS system is set,
write enable for DRAM space
access.
Lower column address strobe Output Lower column address strobe
for 16-bit DRAM space access
Row address strobe 2
Output Row address strobe when
area 2 is designated as DRAM
space.
Row address strobe 3
Output Row address strobe when
area 3 is designated as DRAM
space.
Row address strobe 4
Output Row address strobe when
area 4 is designated as DRAM
space.
Row address strobe 5
Output Row address strobe when
area 5 is designated as DRAM
space.
Upper column address strobe Output Upper column address strobe
for DRAM space access
Wait
Input Wait request signal
Address pins
Output Row address/column address
multiplexed output
Data pins
I/O
Data input/output pins
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