HD6432351 Datasheet, PDF (117/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL)
ISCRH
Bit
:
Initial value:
R/W
:
15
14
13
12
11
10
9
8
IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ISCRL
Bit
:
Initial value:
R/W
:
7
6
5
4
3
2
1
0
IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ISCR registers are 16-bit readable/writable registers that select rising edge, falling edge, or both
edge detection, or level sensing, for the input at pins IRQ7 to IRQ0.
ISCR registers are initialized to H'0000 by a reset and in hardware standby mode.
Bits 15 to 0: IRQ7 Sense Control A and B (IRQ7SCA, IRQ7SCB) to IRQ0 Sense Control A and
B (IRQ0SCA, IRQ0SCB)
Bits 15 to 0
IRQ7SCB to
IRQ0SCB
0
1
IRQ7SCA to
IRQ0SCA
0
1
0
1
Description
Interrupt request generated at IRQ7 to IRQ0 input low level
(initial value)
Interrupt request generated at falling edge of IRQ7 to IRQ0 input
Interrupt request generated at rising edge of IRQ7 to IRQ0 input
Interrupt request generated at both falling and rising edges of
IRQ7 to IRQ0 input
97