HD6432351 Datasheet, PDF (179/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Figure 6-14 shows an example of wait state insertion timing.
By program wait By WAIT pin
T₁
T₂
T_w
T_w
T_w
T₃
ø
WAIT
Address bus
AS
Read
RD
Data bus
Read data
Write
HWR, LWR
Data bus
Write data
Note: indicates the timing of WAIT pin sampling.
Figure 6-14 Example of Wait State Insertion Timing
The settings after a power-on reset are: 3-state access, 3 program wait state insertion, and WAIT
input disabled. When a manual reset is performed, the contents of bus controller registers are
retained, and the wait control settings remain the same as before the reset.
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