HD6432351 Datasheet, PDF (854/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

DMAWER—DMA Write Enable Register
H'FF00
DMAC
Bit
:
7
6
5
4
3
2
1
0
DMAWER : —
—
—
— WE1B WE1A WE0B WE0A
Initial value :
0
0
0
0
0
0
0
0
Read/Write : —
—
—
—
R/W
R/W
R/W
R/W
Write Enable 0A
0 Writes to all bits in DMACR0A,
and bits 8, 4, and 0 in DMABCR
are disabled
1 Writes to all bits in DMACR0A,
and bits 8, 4, and 0 in DMABCR
are enabled
Write Enable 0B
0 Writes to all bits in DMACR0B, bits 9,
5, and 1 in DMABCR, and bit 4 in
DMATCR are disabled
1 Writes to all bits in DMACR0B, bits 9,
5, and 1 in DMABCR, and bit 4 in
DMATCR are enabled
Write Enable 1A
0 Writes to all bits in DMACR1A, and bits
10, 6, and 2 in DMABCR are disabled
1 Writes to all bits in DMACR1A, and bits
10, 6, and 2 in DMABCR are enabled
Write Enable 1B
0 Writes to all bits in DMACR1B, bits 11, 7, and 3 in
DMABCR, and bit 5 in DMATCR are disabled
1 Writes to all bits in DMACR1B, bits 11, 7, and 3 in
DMABCR, and bit 5 in DMATCR are enabled
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