HD6432351 Datasheet, PDF (471/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Examples of Buffer Operation
• When TGR is an output compare register
Figure 10-19 shows an operation example in which PWM mode 1 has been designated for
channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used
in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0
output at compare match B.
As buffer operation has been set, when compare match A occurs the output changes and the
value in buffer register TGRC is simultaneously transferred to timer general register TGRA.
This operation is repeated each time compare match A occurs.
For details of PWM modes, see section 10.4.6, PWM Modes.
TCNT value
TGR0B
TGR0A
H'0000
H'0200
TGR0C H'0200
Transfer
TGR0A
H'0450
H'0200
H'0450
H'0520
H'0450
H'0520
Time
TIOCA
Figure 10-19 Example of Buffer Operation (1)
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