HD6432351 Datasheet, PDF (677/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Section 19 Clock Pulse Generator
19.1 Overview
The H8S/2350 Series has a built-in clock pulse generator (CPG) that generates the system clock
(ø), the bus master clock, and internal clocks.
The clock pulse generator consists of an oscillator circuit, a duty adjustment circuit, a medium-
speed clock divider, and a bus master clock selection circuit.
19.1.1 Block Diagram
Figure 19-1 shows a block diagram of the clock pulse generator.
EXTAL
XTAL
Oscillator
Duty
adjustment
circuit
SCKCR
SCK2 to SCK0
Medium-
speed
divider
ø/2 to ø/32 Bus master
clock
selection
circuit
System clock to ø pin
Internal clock
to supporting
modules
Bus master clock
to CPU, DTC,
and DMAC
Figure 19-1 Block Diagram of Clock Pulse Generator
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