HD6432351 Datasheet, PDF (239/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Bits 10 and 8—Reserved: Can be read or written to.
Bits 7 and 5—Data Transfer Master Enable (DTME): Together with the DTE bit, these bits
control enabling or disabling of data transfer on the relevant channel. When both the DTME bit
and the DTE bit are set to 1, transfer is enabled for the channel.
If the relevant channel is in the middle of a burst mode transfer when an NMI interrupt is
generated, the DTME bit is cleared, the transfer is interrupted, and bus mastership passes to the
CPU. When the DTME bit is subsequently set to 1 again, the interrupted transfer is resumed. In
block transfer mode, however, the DTME bit is not cleared by an NMI interrupt, and transfer is
not interrupted.
The conditions for the DTME bit being cleared to 0 are as follows:
• When initialization is performed
• When NMI is input in burst mode
• When 0 is written to the DTME bit
The condition for DTME being set to 1 is as follows:
• When 1 is written to DTME after DTME is read as 0
Bit 7—Data Transfer Master Enable 1 (DTME1): Enables or disables data transfer on channel
1.
Bit 7
DTME1
0
1
Description
Data transfer disabled. In burst mode, cleared to 0 by an NMI interrupt
Data transfer enabled
(Initial value)
Bit 5—Data Transfer Master Enable 0 (DTME0): Enables or disables data transfer on channel
0.
Bit 5
DTME0
0
1
Description
Data transfer disabled. In normal mode, cleared to 0 by an NMI interrupt (Initial value)
Data transfer enabled
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