HD6432351 Datasheet, PDF (493/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Buffer Operation Timing: Figures 10-40 and 10-41 show the timing in buffer operation.
ø
TCNT
Compare
match signal
TGRA,
TGRB
TGRC,
TGRD
n
n+1
n
N
N
Figure 10-40 Buffer Operation Timing (Compare Match)
ø
Input capture
signal
TCNT
TGRA,
TGRB
TGRC,
TGRD
N
N+1
n
N
N+1
n
N
Figure 10-41 Buffer Operation Timing (Input Capture)
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