HD6432351 Datasheet, PDF (144/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

6.2 Register Descriptions
6.2.1 Bus Width Control Register (ABWCR)
Bit
:
7
ABW7
Modes 1 to 3, 5 to 7*
Initial value :
1
RW
:
R/W
Mode 4
Initial value :
0
RW
:
R/W
6
5
ABW6 ABW5
1
1
R/W R/W
0
0
R/W R/W
4
3
2
ABW4 ABW3 ABW2
1
1
1
R/W R/W R/W
0
0
0
R/W R/W R/W
1
0
ABW1 ABW0
1
1
R/W R/W
0
0
R/W R/W
ABWCR is an 8-bit readable/writable register that designates each area for either 8-bit access or
16-bit access.
ABWCR sets the data bus width for the external memory space. The bus width for on-chip
memory and internal I/O registers is fixed regardless of the settings in ABWCR.
In normal mode, the settings of bits ABW7 to ABW1 have no effect on operation.
After a power-on reset and in hardware standby mode, ABWCR is initialized to H'FF in modes 1,
2, 3, and 5, 6, 7*, and to H'00 in mode 4. It is not initialized by a manual reset or in software
standby mode.
Note: * Modes 2, 3, 6 and 7 only apply to the H8S/2351.
Bits 7 to 0—Area 7 to 0 Bus Width Control (ABW7 to ABW0): These bits select whether the
corresponding area is to be designated for 8-bit access or 16-bit access. In normal mode, only part
of area 0 is enabled, and the ABW0 bit selects whether external space is to be designated for 8-bit
access or 16-bit access .
Bit n
ABWn
0
1
Description
Area n is designated for 16-bit access
Area n is designated for 8-bit access
(n = 7 to 0)
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