HD6432351 Datasheet, PDF (327/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Table 8-9 Number of States Required for Each Execution Status
Object to be Accessed
On-
Chip
RAM
On-
Chip
ROM
On-Chip I/O
Registers
External Devices
Bus width
32
16
8
16
8
16
Access states
1
1
2
2
2
3
2
3
Vector read
Register
information
read/write
S_I —
1
—
—
4
6+2m 2
3+m
S_J 1
—
—
—
—
—
—
—
Byte data read S_K 1
1
2
2
2
3+m 2
3+m
Word data read S_K 1
1
4
2
4
6+2m 2
3+m
Byte data write S_L 1
1
2
2
2
3+m 2
3+m
Word data write S_L 1
1
4
2
4
6+2m 2
3+m
Internal operation S_M 1
The number of execution states is calculated from the formula below. Note that Σ means the sum
of all transfers activated by one activation event (the number in which the CHNE bit is set to 1,
plus 1).
Number of execution states = I · S_I + Σ (J · S_J + K · S_K + L · S_L) + M · S_M
For example, when the DTC vector address table is located in on-chip ROM, normal mode is set,
and data is transferred from the on-chip ROM to an internal I/O register, the time required for the
DTC operation is 13 states. The time from activation to the end of the data write is 10 states.
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