HD6432351 Datasheet, PDF (803/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

Table A-7 Condition Code Modification (cont)
Instruction
ROTXL
ROTXR
RTE
RTS
SHAL
SHAR
SHLL
SHLR
SLEEP
STC
STM
STMAC
HNZ VC
—
0
—
0
—————
—
—
0
—
0
—0
0
—————
—————
—————
Definition
N = Rm
Z = Rm · Rm–1 · ^...... · R0
C = Dm (1-bit shift) or C = Dm–1 (2-bit shift)
N = Rm
Z = Rm · Rm–1 · ^...... · R0
C = D0 (1-bit shift) or C = D1 (2-bit shift)
Stores the corresponding bits of the result.
N = Rm
Z = Rm · Rm–1 · ^...... · R0
V = Dm · Dm–1 + Dm · Dm–1 (1-bit shift)
V = Dm · Dm–1 · Dm–2 · Dm · Dm–1 · Dm–2 (2-bit shift)
C = Dm (1-bit shift) or C = Dm–1 (2-bit shift)
N = Rm
Z = Rm · Rm–1 · ^...... · R0
C = D0 (1-bit shift) or C = D1 (2-bit shift)
N = Rm
Z = Rm · Rm–1 · ^...... · R0
C = Dm (1-bit shift) or C = Dm–1 (2-bit shift)
N = Rm
Z = Rm · Rm–1 · ^...... · R0
C = D0 (1-bit shift) or C = D1 (2-bit shift)
Cannot be used in the H8S/2350 Series
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