HD6432351 Datasheet, PDF (377/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

9.8.2 Register Configuration
Table 9-13 shows the port A register configuration.
Table 9-13 Port A Registers
Name
Abbreviation R/W
Port A data direction register
PADDR
W
Port A data register
PADR
R/W
Port A register
PORTA
R
Port A MOS pull-up control register*² PAPCR
R/W
Port A open-drain control register*² PAODR
R/W
Notes: 1. Lower 16 bits of the address.
2. Only applies to the H8S/2351.
Initial Value
H'00
H'00
Undefined
H'00
H'00
Address*¹
H'FEB9
H'FF69
H'FF59
H'FF70
H'FF77
Port A Data Direction Register (PADDR)
Bit
Initial value
R/W
:
7
6
5
4
3
2
1
0
PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR
:
0
0
0
0
0
0
0
0
:
W
W
W
W
W
W
W
W
PADDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port A. PADDR cannot be read; if it is, an undefined value will be read.
PADDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its
prior state after a manual reset, and in software standby mode. The OPE bit in SBYCR is used to
select whether the address output pins retain their output state or become high-impedance when a
transition is made to software standby mode.
• Modes 1, 2, 3, and 7*
Setting a PADDR bit to 1 makes the corresponding port A pin an output port, while clearing
the bit to 0 makes the pin an input port.
• Modes 4 and 5
The corresponding port A pins are address outputs irrespective of the value of bits PA4DDR to
PA0DDR.
Setting one of bits PA7DDR to PA5DDR to 1 makes the corresponding port A pin an address
output, while clearing the bit to 0 makes the pin an input port.
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