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| HD6432351 Datasheet, PDF (261/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise | |||
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Figure 7-9 illustrates operation in single address mode (when sequential mode is specified).
Address T
Transfer
1 byte or word transfer performed in
response to 1 transfer request
DACK
Address B
Legend
Address T = L
Address B = L + (â1)DTID ⢠(2DTSZ ⢠(Nâ1))
Where : L = Value set in MAR
N = Value set in ETCR
Figure 7-9 Operation in Single Address Mode (When Sequential Mode is Specified)
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