HD6432351 Datasheet, PDF (112/989 Pages) Renesas Technology Corp – The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise

5.1.2 Block Diagram
A block diagram of the interrupt controller is shown in Figure 5-1.
SYSCR
NMI input
IRQ input
INTM1 INTM0
NMIEG
NMI input unit
IRQ input unit
ISR
ISCR IER
Internal interrupt
request
WOVI to TEI
Interrupt controller
Priority
determination
IPR
CPU
Interrupt
request
Vector
number
I, UI
I2 to I0
CCR
EXR
Legend
ISCR : IRQ sense control register
IER : IRQ enable register
ISR : IRQ status register
IPR : Interrupt priority register
SYSCR : System control register
Figure 5-1 Block Diagram of Interrupt Controller
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